The simulation has been carried out using Microwind tool. This flip-flop can reduce 75% of the total power consumption in case of 0% switching activity. The flip-flop circuit does not consume any power when the data input of the flip-flop does not change its state. In the proposed flip-flop only three transistors are connected to the clock signal. ![]() In this method very small number of transistors, only three transistors are connected to clock signal which reduces the power drastically, and the smaller total transistor count assures the same cell area as conventional flip-flops. The transistor which is connected to the clock signal consumes more power. This reduces the number of transistors in the flip-flop. The power reduction is achieved by merging the logically equivalent transistors. A low-power flip-flop named topologically-compressed flip-flop (TCFF) is proposed. ![]() The system uses a technique called Topological- compression technique. TRP Engineering College (SRM GROUP), Tiruchirappalli 621 105, IndiaĪbstract- The proposed system describes the power reduction in flip-flop. Design and Investigation of Power Reduction in D-Flip-Flop
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